Technical Field
The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.
Related Art
As an electrically erasable programmable read-only memory (EEPROM), a split gate semiconductor memory is known.
For example, Japanese Patent Application Laid-Open (JP-A) No. 2004-200181 describes a method of manufacturing a split gate semiconductor memory, and the manufacturing method includes the following steps: a first step of forming a tapered portion serving as a floating gate by etching a polysilicon film using a silicon nitride film as a mask having an opening; a second step of forming a first thermal oxide film on the polysilicon film in the opening of the silicon nitride film; a third step of forming a spacer of a first NSG film covering the tapered portion of the polysilicon film in a side wall of the opening of the silicon nitride film; a fourth step of thermally processing the spacer of the first NSG film so as to form a minute film; a fifth step of forming a spacer of a second NSG film inside the spacer of the first NSG film; a sixth step of forming a polysilicon plug so as to fill the opening of the silicon nitride film and subsequently forming a second thermal oxide film on the polysilicon plug; a seventh step of removing only the silicon nitride film; an eighth step of etching the polysilicon film using the spacer of the first NSG film, the spacer of the second NSG film, and the second thermal oxide film as masks; and a ninth step of removing the spacer of the first NSG film.
On the other hand, JP-A No. 2006-179736 describes a method of manufacturing a split gate memory cell, and the manufacturing method includes the following steps of: forming a floating gate on a semiconductor substrate through an insulating film; forming a source region partially overlapping with the floating gate, on the surface of the semiconductor substrate through the insulating film; forming a tunnel insulating film on the floating gate; forming a control gate on the floating gate and on the semiconductor substrate adjacent to the floating gate through the tunnel insulating film; forming a drain region of a low concentration by injecting impurity ions into the semiconductor substrate using the control gate as a mask; forming a first spacer film in a side wall of the control gate; and forming a drain region of a high concentration by injecting impurity ions into the semiconductor substrate using the first spacer film and the control gate as masks.
The split gate semiconductor memory uses the spacer made of an insulator in order to form the control gate functioning as a word line in a self-aligned manner with respect to the floating gate. The spacer is layered on the floating gate, and is also used in patterning of the floating gate. The control gate is formed by forming a gate member such as polysilicon so as to cover the floating gate and the spacer after the patterning of the floating gate, and being subjected to etch-back processing.
In the conventional manufacturing method, the shape of the gate member at the time of forming the film is influenced by the shape of the spacer so as to be formed in an overhang shape (see FIG. 9B). The insulating film is occasionally provided on the surface of the gate member having the overhang shape, in order to form a peripheral circuit, and the insulating film is formed along the overhang shape of the gate member. In the etch-back processing of the gate member, the insulating film is also etched together with the gate member at the same time. However, the etching of the insulating film progresses slower than the etching of the gate member due to the overhang shape of the gate member. At the time of completion of the etch-back processing, the insulating film is left in a protruding shape, and a protruding portion is occasionally generated in the end portion of the control gate (see FIG. 10B). Subsequently, when a metal compound layer such as a silicide layer is formed on an upper surface of the control gate by a salicide process in order to reduce the resistance of the control gate, the formation of the metal compound layer is hindered due to the generation of the structure of the protruding shape in the control gate, and the control gate is hardly lowered in resistance.